1. Field of the Invention
The present invention relates to a communication device that detects synchronization by using N-phase clocks (N is an integer equal to or greater than two), in particular a communication device that dynamically update a sampling clock of a reception signal.
2. Description of Related Art
An LSI circuit for wireless communication is composed of an LSI circuit for a high frequency (RF) and an LSI circuit for a baseband (BB). The LSI circuit for a high frequency performs analog processing on a signal received through an antenna. The LSI circuit for a baseband performs digital processing on a signal that is not modulated yet or is already demodulated. In high-speed synchronous communication between the LSI circuit for a high frequency and the LSI circuit for a baseband, signal delays and/or jitter occur in the transmission line. The jitter component includes a jitter component occurring in a transmission signal and a jitter component of a clock used on the receiving side. In such a situation, there has been a problem that if these LSI circuits operate independently based on their respective clock signals that are asynchronous to each other, data cannot be correctly received on the LSI circuit on the receiving side. Therefore, to implement correct data reception, the phase of the clock used in data reception on the receiving-side LSI circuit is often controlled.
As a method of controlling the phase of a clock used for data reception in the receiving-side LSI, a technique in which a reception signal having a frame structure is synchronously detected by using N-phase clocks (N is an integer equal to or greater than two) and the optimal phase of the sampling clock is thereby selected based on the synchronous detection result has been under development. A receiving device relating to the present invention is briefly explained hereinafter with reference to FIG. 11.
FIG. 11 is a block diagram showing a configuration of a receiving device relating to the present invention. The receiving device shown in FIG. 11 samples a reception signal by using a frequency n-times as high as the symbol transmission rate. Note that the reception signal has been structured as a frame(s), and the frame includes a synchronous word (Sync Word) area used for synchronization establishment and a payload (Payload) area used to store IQ data as shown in FIGS. 15A and 15B (which are explained later). Synchronous word data that is set in advance by the system is stored in the synchronous word area. In the system, the payload data is transmitted subsequent to the synchronous word data.
An RF unit 202 demodulates a radio signal received through an antenna 201 to generate a data signal, and transmits the generated data signal to a DBD unit 203. A synchronous detection unit 230 samples synchronous word data included in the reception signal by using N-phase clocks (FCLK_P[n−1:0]), and compares the sampling result with a predetermined synchronous pattern. The synchronous detection unit 230 outputs an identification signal (OKFLG) of a clock(s) with which an identical pattern to the predetermined synchronous pattern can be sampled to a clock phase selection unit 240. The clock phase selection unit 240 selects one of these identified clocks as a sampling clock, and outputs its selection signal (CLKSEL[n−1:0]) to an FIFO unit 280. A clock transfer processing 270 receives a data signal output from the synchronous detection unit 230 using the N-phase clock, and transfers the received data signal to a reference clock (FCLK_M). The FIFO unit 280 receives payload data subsequent to the synchronous word data by using the selected sampling clock. A PLL (Phase Locked Loop) circuit 250 generates a plurality of clocks (FCLK_P[n−1:0]) each of which has a different phase from that of the reference clock (FCLK_M). A signal processing circuit 290 processes the signal that is received in this manner.
Further, as a technique relating to the present invention, Japanese Unexamined Patent Application Publication No. 7-321646, for example, discloses a phase decision circuit that selects a suitable sampling clock from N-phase clocks according to a variation point of a reception signal on which the decision is to be made. The phase decision circuit in accordance with Japanese Unexamined Patent Application Publication No. 7-321646 is briefly explained hereinafter with reference to FIGS. 12 and 13.
FIG. 12 is a circuit diagram showing a configuration of a phase decision circuit in accordance with Japanese Unexamined Patent Application Publication No. 7-321646. As shown in FIG. 12, the phase decision circuit includes a sampling unit 301 that detects a bit boundary, which is a variation point of a reception signal, a decision protection unit 302 that retains information about the detected bit boundary, a phase decision unit 303, a clock selection unit 304, and a synchronization protection unit 305.
The sampling unit 301 operates by using a clock four times as fast as the sampling rate, for example, and uses four-phase clocks C0, C1, C2 and C3. The sampling unit 301 receives a reception signal by using these four-phase clocks in an input sampling circuit 311 (D-type flip-flops 411 to 414). Then, four received data A, B, C and D are compared in an arithmetic circuit 312 (EORs 421 to 424), and a calculation result indicating a variation point of the reception signal is retained in a phase adjustment circuit 313 (D-type flip-flops 431 to 434). Note that the output signal of the arithmetic circuit 312 is readjusted in timing in the phase adjustment circuit 313, and transmitted as flag signals E, F, G and H indicating the variation point of the reception signal to the decision protection unit 302.
The decision protection unit 302 includes JK-type flip-flops 511 to 514 corresponding to respective four-phase clocks, and protects variation point information of the reception signal until a count value counted in a count unit 515 reaches a predefined number. The decision protection unit 302 is reset to the initial value when the count value reaches the predefined number in the count unit 515, and obtains variation point information of the reception signal from the sampling unit 301 again.
The phase decision unit 303 distinguishes the phase state of each clock based on the protected variation-point information of the reception signal, and determines which clock signal is most suitable. The clock selection unit 304 selects the optimal sampling phase from the four-phase clocks according to the phase decision result in the phase decision unit 303.
The synchronization protection unit 305 detects out-of-synchronization when the variation point of the reception signal moves and the relation between the reception signal and the determined phase is not thereby optimal. In this way, even when the reception signal is unstable, the sampling phase is selected so that the sampling phase dynamically follows the variation point of the reception signal.
FIG. 13 is operation waveforms of the phase decision circuit in accordance with Japanese Unexamined Patent Application Publication No. 7-321646. In the example shown in FIG. 13, the input sampling circuit 311 outputs signals shown as FIGS. 13(a) to 13(i) by sampling a reception signal by using the clock signals C0 to C3. The arithmetic circuit 312 outputs signals shown as FIGS. 13(g) to 13(j) by calculating the exclusive-OR of these output signals. The phase adjustment circuit 313 outputs signals shown as FIGS. 13(k) and 13(l) by sampling the signals shown as FIGS. 13(g) to 13(j) again by using the clock capable of catching “1” level of the waveform with certainty. In the example shown in FIG. 13, the phase decision unit 303 can determine that the variation point of the reception signal is located between C0 and C1, and therefore the clock C3, for example, is determined to be the optimal phase.